BEGIN:VCALENDAR VERSION:1.0 BEGIN:VEVENT SUMMARY:RF System Level Design and Verification DESCRIPTION;ENCODING=QUOTED-PRINTABLE:"RF System Level Design and Verification" Buenaventura MTT-S Chapter. Jose Luis Pino of Agilent Technologies. Contact g.earnest@ieee.org DTSTART:20050216T183000 DTEND:20050216T193000 END:VEVENT END:VCALENDAR